1. Field of the Invention
The present invention relates to a semiconductor memory and more particularly, to a memory provided with at least a serial access port.
2. Description of the Related Art
With the progress in memory technology, dual-port memories equipped with a plurality of ports on one semiconductor chip have been developed and put into partical application in place of a conventional single-port memories. Since such a dual-port memory has a plurality of output ports on a single semiconductor chip, it has a large advantage in that a plurality of data can be processed asynchronously. In the field of image processing which has made a remarkable progress in recent years, for example, this dual port memory is used as a memory (referred to as a "video memory") for holding image data. The dual-port memory of this kind includes a random access port and a serial access port on the single chip. The random access port is the same as the port provided to a conventional RAM (Random Access Memory). Through this port, one bit is read from or written into each randomly accessed memory cell in the case of a 1-bit output type memory, while in the case of a memory for multi-bit parallel output type, the port is used to read or write a plurality of bits at a time. On the other hand, the serial access port usually has a buffer (hereinafter referred to as "line buffer") corresponding to the number of bits of one word is used to simultaneously receive all the bits in the memory cells connected to the word line selected in accordance with row address information in the cell array and output them serially to the outside.
In such a dual-port memory used as a video memory, the random access port and the serial access port can be used asynchronously so that the read/write of image data between CPU and the video memory and the readout of display data from the video memory to a display (such as a CRT or a liquid crystal display) can be made asynchronously. Therefore, the dual-port memory can greatly contribute to the improvement in processing efficiency of CPU, high speed display/simplification of display processing and digitallization of TV, VTR, and the like.
In the above dual port memory, the serial access port includes a word data latch circuit (hereinafter referred to as the "line buffer") for holding data derived from one selected word, a serial selection circuit for serially selecting data stored in the line buffer one by one, and a serial port for outputting data designated by the serial selection circuit. In order to accomplish practically the dual port memory having a large memory capacity such as 256 K bits or 1 Mega bits, whole memory cells are splited into a plurality of memory planes. Each of the memory planes is provided with a random access port and a serial access port which includes a line buffer, a serial selection circuit and a serial output circuit. Among the plurality of memory planes, one memory plane is selectively enabled while the remaining other memory planes are disenabled. However, as the number of the memory planes is increased, the number of line buffers as the nuclei of the dual-port memory must be increased in proportion to the number of memory planes. Therefore, though the total area of the cell array does not much change as a whole due to division into the memory planes, the occupying area of the line buffers increases in proportion to the number of the division. As a result, the problem develops in that the memory cell capacity is limited. Particularly because the serial access port having the line buffer must be able to operate asynchronously with the random access port, static type latch circuits not requiring refresh are preferably used for the line buffer even if dynamic memory transistors are used for the memory cells in the array. However, the area necessary for the static latch circuits is by far greater than that of the dynamic latch circuits.
Moreover, in the conventional dual port memory, the bit number of the line buffer is required to be the number of the memory cells which are selected at each access cycle, in each of the memory plane. Thus, as a whole, the bit number in all the line buffers is remarkably large even they are not used simultaneously.